Automated Extraction of Multi-Threaded Graph Models for Formal Verification of System Level Models

System level models are abstractions of hardware systems which should make it easier to apply capacity limited formal verification tools to validate them. However, due to the sequential nature of languages such as SystemC [1], extensive use of co-routine style threading for expressing concurrency, and oft-used mixed abstraction styles, make it hard to create abstractions suitable for formal verification tools. Especially for system engineers such model abstraction is more difficult than formal methods experts. In this paper we describe our methodology of automated extraction of system models to Multi-threaded Graph (MTG) models followed by automated transformation into formal models suitable for the UPPAAL formal verification tool. This allows engineers to semi-automatically capture the intrinsic concurrency, event model, synchronization aspects, and timing aspects in a system model, and automatically create a formal model from there. We have developed scripting based tools that can accept a SystemC class model, and convert it into an MTG model represented with XML, and then translate this model into UPPAAL models. The automated conversion tools being in experimental stages, in this paper we describe the methodology and detail the conversion schemes from MTG models to UPPAAL models and illustrate with a simple example. ! " # $% & ' ( Syed M. Suhaib, IEEE Student Member and Sandeep K. Shukla, IEEE Senior Member {ssuhaib, shukla}@vt.edu Automated Extraction of Multi-Threaded Graph Models for Formal Verification of System Level Models Syed M. Suhaib Sandeep K. Shukla FERMAT LAB Bradley Department of Electrical and Computer Engineering Virginia Tech Blacksburg, VA 24060, USA email:{ssuhaib, shukla} @vt.edu